A high speed analog Decision Feedback Equalization (DFE) can be achieved by providing fast direct h1 feedback, and generally requires fast direct h1 feedback to avoid having to implement an unrolled h1 DFE architecture, which requires more power and circuit area. However, the timing of the direct h1 feedback must be fast enough for the DFE to properly equalize the channel at the required data rates. A DFE circuit consists a summing circuit, which sums the different DFE feedback taps with the input analog data, followed by a sampling circuit that contains a bank of sampling or capture latches. Each capture latch also functions as a voltage comparator that can have different voltage thresholds. The output of the sample latch in the sampling block provides the h1 tap feedback to the summing circuit.
Conventional capture latch designs consist of a strong-arm latch, whose outputs reset to a reference voltage, such as AVCC, every half sample clock cycle, followed by a second latch to convert the strong-arm latch outputs to Non-Return-to-Zero (NRZ) output levels. However, the combined clock-to-q delay of the strong-arm latch with the NRZ latch is too slow to meet the direct h1 feedback timing for fast data rates, such as a 56 Gbit data rate.
Accordingly, circuits and methods that improve the performance of a differential feedback equalizer are beneficial.